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data sheet, v2.0, december 2003 never stop thinking. hye18p32160ac(-/l)9.6 hye18p32160ac(-/l)12.5 hye18p32160ac(-/l)15 32m synchronous burst cellularram cellularram memory products
edition 2003-12-16 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2004. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in lif e-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safe ty or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
never stop thinking. hye18p32160ac(-/l)9.6 hye18p32160ac(-/l)12.5 hye18p32160ac(-/l)15 32m synchronous burst cellularram cellularram data sheet, v2.0, december 2003 memory products
template: mp_a4_v2.0_2003-06-06.fm hye18p32160ac(-/l)9.6, hye18p32160ac(-/l)12.5, hye18p32160ac(-/l)15 revision history: 2003-12-16 v2.0 previous version: 1.8, 1.9 (target data sheet) page subjects (major changes since last revision) all converted to new datasheet template all addition of part numbered 12.5 which is the combination of 70ns asynch and 80mhz burst speed 22 change of pasr range setting : remove 3/4, then add 1/8 31-33 remove wait timing and parameter definition from asynchronous read all 2nd bin of icc2 added. marking for low-power part puts ?l? in the place of ?-? all (synch) no negative (falling) edge of clk configuration supported all (synch) adv hold time from clk added for burst operation all (synch) taclk relaxed to 7ns for grade of 9.6 all (synch) thd relaxed to 1.5ns for grade of 9.6 all tlz, tblz, tolz are adjusted all s/w register entry mode is officially supported and specified we listen to your comments any information within this document that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com
data sheet 5 v2.0, 2003-12-16 hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3 hye18p32160ac(-/l)9.6/12.5/15 ball configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 1.4 hye18p32160ac(-/l)9.6/12.5/15 ball definition and description . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.5 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.6 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.6.1 commands supported in sram-type mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.6.2 commands supported in nor-flash-type mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.6.3 commands supported in synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.1 power-up and initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2 access to the control register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3 refresh control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.1 partial array self refresh (pasr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.2 deep power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3.3 temperature compensated self refresh (tcsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3.4 power saving potential in standby when applying pasr, tcsr or dpd . . . . . . . . . . . . . . . . . . . 23 2.3.5 page mode enable/disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.4 bus control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.4.1 latency modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.4.2 read burst configurations/sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.4.3 wait signal in synchronous burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.4.4 hold data out mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.5 self-refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.6 sram-type mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.6.1 asynchronous read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.6.2 page mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.6.3 asynchronous write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.7 nor-flash-type mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.7.1 synchronous read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.7.2 burst suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.7.3 asynchronous write with address latch (adv ) control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.8 synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.8.1 synchronous read mode including burst suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.8.2 synchronous write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.9 general ac input/output reference waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.2 recommended power & dc operation ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 3.3 output test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.4 pin capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5 appendix a: low-frequency mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.1 asynchronous access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6 appendix b: s/w register entry mode (?4-cycle method?) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table of contents
data sheet 6 v2.0, 2003-12-16 hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram figure 1 cellularram - interface configuration options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 2 standard ballout - hye18p32160ac(-/l)9.6/12.5/15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 3 functional block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 4 power up sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 5 the two control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 6 control register write in sram-type mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 7 control register write in nor-flash-type mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 8 control register write in synchronous mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 9 pasr programming scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 10 pasr configuration example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 11 latency mode - functional diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 12 data out configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 13 asynchronous read - address controlled (cs = oe = v il , we = v ih , ub and/or lb = v il , cre = v il, adv = v il ) 31 figure 14 asynchronous read (we = v ih , cre = v il ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 15 asynchronous page read mode (cre = v il, adv = v il ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 16 asynchronous write - we controlled (oe = v ih or v il , cre = v il ) . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 17 asynchronous write - cs controlled (oe = v ih or v il , cre = v il ). . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 18 asynchronous write - ub , lb controlled (oe = v ih or v il , cre = v il ) . . . . . . . . . . . . . . . . . . . . . 35 figure 19 asynchronous write to control register (oe = v ih or v il ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 20 synchronous read burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 21 burst suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 22 asynchronous write with address latch (adv ) control (followed by single-burst read) . . . . . . . . 40 figure 23 asynchronous write with address latch (adv ) control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 24 asynchronous write to control register in nor-flash mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 25 synchronous write burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 26 synchronous write to control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 27 synchronous write burst followed by synchronous read burst. . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 28 synchronous read burst followed by synchronous write burst. . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 29 output test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 30 p-vfbga-54 (plastic very thin fine pitch ball grid array package) . . . . . . . . . . . . . . . . . . . . . . 49 figure 31 low-frequency mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 32 s/w register entry timing (address input = 1fffffh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1 figure 33 rcr mapping in s/w register entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 34 bcr mapping in s/w register entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 list of figures
data sheet 7 v2.0, 2003-12-16 hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram table 1 product selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2 ball description - hye18p32160ac(-/l)9.6/12.5/15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3 asynchronous command table (sram-type mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 4 description of commands (sram-type mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 5 asynchronous command table (nor-flash-type mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 6 synchronous command table (nor-flash-type mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 7 description of commands in nor-flash type mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 8 synchronous command table (full synchronous mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 9 description of commands in synchronous mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 10 standby currents when applying pasr, tcsr or dpd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 11 latency mode configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 12 burst sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 13 timing parameters - asynchronous read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 14 timing parameters - asynchronous write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 15 timing parameters - synchronous read burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 16 timing parameters - asynchronous write with adv control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 17 timing parameters - synchronous read/write burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 18 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 19 recommended dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 20 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 22 pin capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 21 operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 list of tables
data sheet 8 v2.0, 2003-12-16 32m synchronous burst cellularram cellularram hye18p32160ac(-/l)9.6 hye18p32160ac(-/l)12.5 hye18p32160ac(-/l)15 1overview 1.1 features high density (1t1c-cell) synchronous 32-mbit pseudo-static ram designed for cell phone applications (cellularram) functional-compatible (asynchronous mode) to conventional low power asynchronous sram devices organization 2m 16 refresh-free operation 1.8 v single power supply ( v dd and v ddq ) low power optimized design ? i standby = 90 a (for l-part 1) ) or 120ua (for standard part), data retention mode ? i dpd = < 25 a (32m), non-data retention mode low power features (partly adopted from the jedec standardized low power sdram specifications) ? temperature compensated self-refresh (tcsr) ? partial array self-refresh (pasr) ? deep power down mode (dpd) user configurable interface supporting three different access protocols (values from 9.6 part) ? asynchronous sram protocol, 70 ns random access cycle time, 20 ns page mode (read only) cycle time ? nor-flash burst protocol, 70 ns write cycle time, 104 mhz burst mode read cycle ? synchronous (bi-directional) interface protocol, 70 ns random cycle time, 104 mhz burst mode read/write cycle in nor-flash burst or in synchronous mode the additional user settings are featured ? programmable fixed burst length of 4/8/16 words or continuous burst mode ? programmable latency modes to adjust the desired burst frequency ? wrap mode function ? programmable wait signal polarity and timing byte read/write control by ub /lb (asynchronous mode and in synchronous burst read) synchronous data input mask function supported by ub /lb in synchronous burst write mode wireless operating temperature range from -25 c to +85 c p-vfbga-54 chip-scale package (9 6 ball grid) table 1 product selection hye18p32160ac l9.6 1) 1) contact factory -9.6 l12.5 1) -12.5 l15 1) -15 maximum input clk frequency (mhz) lat = 2 66 50 40 lat = 3 104 80 66 min. random cycle time ( t rc ) 70 ns 70 ns 85 ns stand-by current ( i cc2 )90 a 120 a90 a120 a90 a 120 a hye 18 p 3216 0 a c chip scale package design revision number device type 32m (x16 org) v dd = 1.8 v typ. psram product 0: standard (54-ball) extended temp. part
data sheet 9 v2.0, 2003-12-16 hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram overview 1.2 general description the 32m synchronous burst cellularram (cellularram) is designed to meet the growing memory density and bandwidth demand in 3g cellular phone designs. its high density 1t1c-cell concept, the multi-protocol interface capabilities, its highly optimized low power design and its refresh-free operation make the cellularram the perfect fit for 3g baseband applications. configured in synchronous burst mode, a peak bandwidth of > 200 mbyte/s is achieved at the max. clock rate of 104 mhz. the burst length can be programmed and set to either fixed burst lengths of 4, 8- or 16-words 1) or set to continuous mode. the 16-word burst mode is specially designed for cached processor designs to speed up cache re-fill operations. in nor-flash, burst mode read accesses are synchron ous whereas write accesses are of asynchronous nature. this is to retain compatibility to today?s nor-flash pr otocols and thus to make sure that existing baseband designs do get instantly a performance gain in read direction by deploying the nor-flash burst protocol. the different access protocols that are supported by the cellularram are illustrated in figure 1 . data byte control (ub , lb ) is featured in all modes and provides dedicated lower and upper byte access. figure 1 cellularram - interface configuration options the cellularram can be operated from a single 1.8 v power supply feeding the core and the output drivers. the chip is fabricated in infineon technologies advanced low power 0.14 m process technology and comes in a p-vfbga-54 package. 1) 1 word is equal 16 bits /cs /we /oe 32mb cellularram (fbga-54) sram i/f read: async/ page sync. burst sync burst write: async async w/ adr latch sync burst 32mb cellularram (fbga-54) nor-flash i/f 32mb cellularram (fbga-54) sync. i/f /cs /we /oe clk /adv wait clk /adv wait 32mb cellularram (fbga-54) /cs /we /oe /ub /lb clk /adv cre a20-a0 dq15-dq0 32mb cellularram (fbga-54) /cs /we /oe /ub /lb cre a20-a0 dq15-dq0 wait asynchronous i/f sync. burst i/f & nor-flash burst & asynchronous i/f pinning: protocols: /cs /we /oe clk=/adv=low and wait ignored in asynchronous i/f
hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram overview data sheet 10 v2.0, 2003-12-16 1.3 hye18p32160ac(-/l)9.6/12.5/15 ball configuration figure 2 standard ballout - hye18p32160ac(-/l)9.6/12.5/15 note: figure 2 shows top view 123 d b c e f g a0 a 6 45 dq8 lb# a1 oe# ub# a2 cre a3 a4 cs# dq0 dq9 dq10 a5 a6 dq1 dq2 dq3 a7 dq11 dq12 a16 a14 a15 v dd a12 dq15 dq4 a13 dq5 dq6 we# dq7 v ddq h j a8 v ss a9 a10 clk adv# a11 a20 nc nc nc (a21) v ssq wait a17 dq14 dq13 a19 a18 nc (a22)
data sheet 11 v2.0, 2003-12-16 hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram overview 1.4 hye18p32160ac(-/l)9.6/12.5/15 ball definition and description table 2 ball description - hye18p32160ac(-/l)9.6/12.5/15 ball type detailed function clk input clock signal in synchronous burst mode, address and command inputs and data are referenced to clk. in asynchronous sram-type mode the clock signal is ignored. during write accesses in nor-flash operation mode the clk signal must be clamped to low. cre input control register enable cre set to high enables the access to the control register map. by applying the set control register (scr) command (see table 3 ) the address bus is loaded into the selected control register. adv input address valid adv signals in nor-flash and full synchronous mode that a valid address is present on the address bus. in nor-flash read mode and full synchronous mode the address is latched on the programmed clock edge while adv is held low. in nor-flash write mode adv can be used to latch the address, but can be held low as well. in asynchronous sram-type mode adv needs to be active, it may be tied to active. cs input chip select cs enables the command decoder when low and disables it when high. when the command decoder is disabled new commands are ignored, addresses are don?t care and outputs are forced to high-z. internal operations, however, continue. for the details please refer to the command tables in chapter 1.6 . oe input output enable oe controls dq output driver. oe low drives dq, oe high sets dq to high-z. we input write enable we set to low while cs is low initiates a write command. ub , lb input upper/lower byte enable ub enables the upper byte dq15-8 (resp. lb dq7 ? 0) during read/write operations. ub (lb ) deassertion prevents the upper (lower) byte from being driven during read or being written. wait output 3-state wait state signal in synchronous mode, wait signal indicates the host system when the output data is valid during read and when the input data should be asserted during write operation. in asynchronous mode, the signal has to be ignored. a <20:0> input address inputs during a control register set operation by cre access, the address inputs define the register settings. dq <15:0> i/o data input/output the dq signals 0 to 15 form the 16-bit data bus. 1 v dd 1 v ss power supply power supply, core power and ground for the internal logic. 1 v ddq 1 v ssq power supply power supply, i/o buffer isolated power and ground for the output buffers to provide improved noise immunity. 4 nc ? no connect please do not connect. reserved for future use, i.e. e3: a21, j4: a22, see ballout in figure 2 on page 10 .
hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram overview data sheet 12 v2.0, 2003-12-16 1.5 functional block diagram figure 3 functional block diagram address decode async/ page i/f 1t1c-cell memory array (2m x16) mux control logic cs we oe ub lb clk adv cre a 20-a0 dq7-dq0 sync. burst i/f wait additional pins necessary to operate the device in nor-flash and synchronous mode nor-flash burst i/f dq15-dq8
data sheet 13 v2.0, 2003-12-16 hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram overview 1.6 commands the supported command set depends on the selected operation mode. by default the cellularram device is reset to the asynchronous sram-type mode after power-up. to put the device in a different operation mode the bus configuration register must be programmed first accordingly. the valid control input states and sequences are listed below for the different operation modes. other control signal combinations are not supported. 1.6.1 commands supported in sram-type mode in the sram-type operation mode all commands are of asynchronous nature. table 3 lists the asynchronous commands supported in sram-type mode. clk has to be held low for entire asynchronous mode operation. note: ?l? represents a low voltage level, ?h? a high voltage level, ?x? represents ?don?t care?, ?v? represents ?valid?. table 3 asynchronous command table (sram-type mode) operation mode power mode cs adv we oe ub / lb cre a19 a20 - a0 dq15:0 read active l l h l l 1) 1) table 3 reflects the behaviour if ub and lb are asserted to low. if only either of the signals, ub or lb , is asserted to low only the corresponding data byte will be output or written (ub enables dq15 - dq8, lb enables dq7 - dq0). lvadr dout write active lllx 2) 2) during a write access invoked by we set to low the oe signal is ignored. l 1) lvadr din set control register active lllx 2) xhl h rcr din bcr din x no operation standby~active 3) 3) stand-by power mode applies only to the case when cs goes low from deselect while no address change occurs. toggling address results in active power mode. also, no operation from any active power mode by keeping cs low consumes the power higher than stand-by mode. l xhhxl xx high-z deselect st andby h x x x xxxx high-z dpd 4) 4) deep power down is maintained until control register is re-programmed to disable dpd control bit (rcr bit 4). deep power down h x x x xxxx high-z table 4 description of commands (sram-type mode) mode description read the read command is used to perform an asynchronous read cycle. the signals, ub and lb , define whether only the lower, the upper or the whole 16-bit word is output. write the write command is used to perform an asynchronous write cycle. the data is latched on the rising edge of either cs , we , ub , lb , whichever comes first. the signals, ub and lb , define whether only the lower, the upper or the whole 16-bit word is latched into the cellularram. set control register the control registers are loaded via the address inputs a19, a15 - a0 performing an asynchronous write access. please refer to the control register description for details. the scr command can only be issued when the cellularram is in idle state. no operation the nop command is used to perform a no operation to the cellularram, which is selected (cs = 0). operations already in progress are not affected. power consumption of this command mode varies by address change and initiating condition.
hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram overview data sheet 14 v2.0, 2003-12-16 1.6.2 commands supported in nor-flash-type mode in nor-flash-type mode read commands are performed on a synchronous base whereas write commands are performed in an asynchronous way. in synchronous read mode all operations are defined by the states of the control signals cs , adv , oe , we and ub , lb at the positive (default) edge of the data clock. to put the device in nor-flash-type mode the bus configuration register must be programmed first accordingly. table 5 lists the truth table for the supported asynchronous write commands, while table 5 lists the supported synchronous read commands. note: ?l? represents a low voltage level, ?h? a high voltage level, ?x? represents ?don?t care?, ?v? represents ?valid?. deselect the deselect function prevents new commands from being executed by the cellularram. the cellularram is effectively deselected. i/o signals are put to high impedance state. dpd dpd stops all refresh-related activities and entire on-chip circuit operation. current consumption drops below 25 a. wake-up from dpd also requires 150 s to get ready for normal operation. table 5 asynchronous command table (nor-flash-type mode) operation mode power mode cs adv we oe ub / lb cre a19 a20 - a0 dq15:0 write active lllx 1) 1) during a write access invoked by we set to low the oe signal is ignored. l 2) 2) table 5 reflects the behaviour if ub and lb are asserted to low. if only either of the signals, ub or lb , is asserted to low only the corresponding data byte will be output or written (ub enables dq15 - dq8, lb enables dq7 - dq0). lvadr din set control register active lllx 1) xhl h rcr din bcr din x no operation standby~active 3) 3) stand-by power mode applies only to the case when cs goes low from deselect while no address change occurs. no operation from any active power mode by keeping cs low consumes the power higher than stand-by mode. l hhhxl xx high-z deselect st andby h x x x x l x x high-z dpd 4) 4) deep power down is maintained until control register is re-programmed to disable the bit for deep power down (rcr bit 4). deep power down h x x x x x x x high-z table 6 synchronous command table (nor-flash-type mode) operation mode power mode clk cs adv we ub / lb 1) 1) oe does the same function to all dq pins with ub and lb during read operation. cre a20 - a0 dq15:0 burst init active l->h l l h x l adr x burst read active l->h l h h l 2) 2) table 6 reflects the behaviour if ub and lb are asserted to low. if only either of the signals, ub or lb , is asserted to low only the corresponding data byte will be output or written (ub enables dq15 - dq8, lb enables dq7 - dq0). if both signals are disabled the device is put in deselect mode. lx dout 3) no operation standby~active 4) l->h l h h x l x high-z 5) deselect sta ndby l->h h xxxxx high-z dpd 6) deep power downl hxxxxx high-z table 4 description of commands (sram-type mode) (cont?d) mode description
data sheet 15 v2.0, 2003-12-16 hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram overview note: ?l? represents a low voltage level, ?h? a high voltage level, ?x? represents ?don?t care?, ?v? represents ?valid?. 3) output driver controlled by the asynchronous oe signal 4) stand-by power mode applies only to the case when cs goes low from deselect while no address change occurs. no operation from any active power mode by keeping cs low consumes the power higher than stand-by mode. 5) the asynchronous oe control signal has to be asserted to ?h?. 6) deep power down is maintained until control register is re-programmed to disable the bit for deep power down (rcr bit 4). table 7 description of commands in nor-flash type mode mode description write the write command is used to perform an asynchronous write cycle. while the address is latched by the rising edge of adv , the data is latched by the rising edge of either cs , we , ub , lb , whichever comes first. the signals, ub and lb , define whether only the lower, the upper or the whole 16-bit word is latched into the cellularram. burst init the burst init command is used to initiate a synchronous burst read access and to latch the burst start address. the burst length is determined by the bit2 - bit0 in the bus configuration register. burst read the burst read command is used to perform a synchronous burst read access. the first data is output after the number of clock cycles as defined by the programmed latency mode. set control register the control registers are loaded via the address inputs a19, a15 - a0 performing an asynchronous nor-flash type write access. please refer to the control register description for details. the scr command can only be issued when the cellularram is in idle state and no bursts are in progress. no operation the nop command is used to perform a no operation to the cellularram, which is selected (cs = 0). operations already in progress are not affected. deselect the deselect function prevents new comm ands from being executed by the cellularram. the cellularram is effectively deselected. i/o signals are put to high impedance state. dpd dpd stops all refresh-related activities and entire on-chip circuit operation. current consumption drops below 25 a. wake-up from dpd also requires 150 s to get ready for normal operation.
hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram overview data sheet 16 v2.0, 2003-12-16 1.6.3 commands supported in synchronous mode in bi-directional synchronous mode read and write operations are performed on a complete synchronous base. to put the device in full synchronous mode the bus configuration register must be programmed first accordingly. table 8 shows the truth table for the supported synchronous read/write commands. note: ?l? represents a low voltage level, ?h? a high voltage level, ?x? represents ?don?t care?, ?v? represents ?valid?. table 8 synchronous command table (full synchronous mode) operation mode power mode clk cs adv we ub / lb 1) 1) oe does the same function to all dq pins with ub and lb during read operation. cre a19 a20 - a0 dq15:0 burst init read active l->hllhxlvadr x burst read active l->h l h x l 2) 2) table 8 reflects the behaviour if ub and lb are asserted to low. if only either of the signals, ub or lb , is asserted to low only the corresponding data byte will be output or written (ub enables dq15 - dq8, lb enables dq7 - dq0). if both signals are disabled the device is put in deselect mode. xxx dout 3) 3) output driver controlled by the asynchronous oe control signal burst init write active l->hlllxlvadr x burst write active l->h l h x l 2) xxx din set control register active l->h l l l x h l h rcr din bcr din x no operation standby~active 4) 4) stand-by power mode applies only to the case when cs goes low from deselect while no address change occurs. no operation from any active power mode by keeping cs low consumes the power higher than stand-by mode. l->h l h h x l x x high-z 5) 5) the asynchronous oe control signal has to be asserted to ?h?. deselect st andby l->h h x x x x x x high-z dpd 6) 6) deep power down is maintained until control register is re-programmed to disable the bit for deep power down (rcr bit 4). deep power down l h x x x x x x high-z table 9 description of commands in synchronous mode mode description burst init the burst init command is used to initiate a synchronous burst access and to latch the burst start address. the burst length is determined by the setting in the bus configuration register. burst read the burst read command is used to perform a synchronous burst read access. the first data is output after the number of clock cycles as defined by the programmed latency mode. burst write the burst write command is used to perform a synchronous burst write access. the point of time when the first data is written is indicated by the wait signal. it varies with the selected clock frequency and the occurrence of a refresh cycle. set control register the control registers are loaded via the address inputs a19, a15 - a0 performing a single word burst. please refer to the control register description for details. the scr command can only be issued when the cellularram is in idle state and no bursts are in progress. no operation the nop command is used to perform a no operation to the cellularram, which is selected (cs = 0). operations already in progress are not affected.
data sheet 17 v2.0, 2003-12-16 hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram overview deselect the deselect function prevents new comm ands from being executed by the cellularram. the cellularram is effectively deselected. i/o signals are put to high impedance state. dpd dpd stops all refresh-related activities and entire on-chip circuit operation. current consumption drops below 25 a. wake-up from dpd also requires 150 s to get ready for normal operation. table 9 description of commands in synchronous mode (cont?d) mode description
hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram functional description data sheet 18 v2.0, 2003-12-16 2 functional description 2.1 power-up and initialization the power-up and initialization sequence guarantees that the device is preconditioned to the user?s specific needs. like conventional drams, the cellularram must be powered up and initialized in a predefined manner. v dd and v ddq must be applied at the same time to the specified voltage while the input signals are held in ?deselect? state (cs = high). after power on, an initial pause of 150 s is required prior to the control register access or normal operation. failure to follow these steps may lead to unpredictable start-up modes. please note the default operation mode after power up is the asynchronous sram i/f mode (see chapter 2.4 ). figure 4 power up sequence v dd, vddq t pu =150 s ready for normal operation vdd,vddq,min
data sheet 19 v2.0, 2003-12-16 hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram functional description 2.2 access to the control register map write-only access to the control register map is enabled by applying the scr command asserting the cre-pin to high. in combination with cre set to high, pin a19 designates the operation to one of either control registers. pin a19 set to low selects the refresh control regi ster (rcr), pin a19 set to high addresses the bus configuration register (bcr). write and read access to the control registers is also available at s/w entry method. for details, please refer to ?appendix b: s/w register entry mode (?4-cycle method?)? on page 51 . figure 5 the two control registers figure 6 control register write in sram-type mode burst length a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 bw 0 0 wp wc imp 0 om latency mode a19 1 a16 0 a17 0 a18 0 a20 0 pasr a0 a1 a2 a3 a4 a5 a6 a7 a8 a18 a20 tcsr pm 0 0 0 dpd 0 a19 0 0 0 0 0 0 0 0 0 0 a9 a10 a11 a12 a13 a14 a15 a16 a17 a19 is the selection address between bcr and rcr bus control register bcr refresh control register rcr all '0' are reserved bits and must be set to zero. 0 1 (bcr.a6 has to be set to one) don't care a 20-a0 opcode cs we ub, lb dqx cre a19 initiate control register access latch opcode on address address bcr adv (latch opcode) write opcode 0(rcr), 1(bcr)
hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram functional description data sheet 20 v2.0, 2003-12-16 figure 7 control register write in nor-flash-type mode figure 8 control register write in synchronous mode don't care a20-a0 opcode cs we ub, lb d q15-dq0 adv address cre a19 initiate control register access write latched opcode to selected control register select control register open address bus latch close address bus latch 0(rcr), 1(bcr) don't care cs oe ub, lb we d q15-dq0 a20-a0 opcode clk wait adv cre a19 initiate control register access latch control register address latch control register value 0(rcr),1(bcr)
data sheet 21 v2.0, 2003-12-16 hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram functional description 2.3 refresh control register the refresh control register (rcr) allows to save stand-by power additionally by making use of the temperature-compensated self refresh (tcsr), partial-array self refresh ( pasr) and deep power down (dpd) features. the refresh control register is pr ogrammed via the control register set command (with cre = 1 and a19 = 0) and retains the stored information until it is reprogrammed or the device loses power. please note that the rcr contents can only be set or changed when the cellularram is in idle state. rcr refresh control register (cre, a19 = 10 b ) a20a19a18a17a16a15a14a13a12a11a10a9a8a7a6a5a4a3a2a1a0 0 rs 0 pm tcsr dpd 0 pasr field bits type 1) description rs 19 w register select 0 set to 0 to select this rcr (= 1 to select bcr). pm 7 w page mode enable/disable in asynchronous operation mode the user has the option to toggle a0 - a3 in a random way at higher rate (20 ns vs. 70 ns) to lower access times of subsequent reads with 16-word boundary. in synchronous mode this option has no effect. the max. page length is 16 words. please note that as soon as page mode is enabled the cs low time restriction applies. this means that the cs signal must not be kept low longer than t csl = 10 s. please refer to figure 15 . 0 page mode disabled (default) 1 page mode enabled tcsr [6:5] w temperature compensated self refresh the 2-bit wide tcsr field features four different temperature ranges to adjust the refresh period to the actual case temperature. since dram technology requires higher refresh rates at higher temperature this is a second method to lower power consumption in case of low or medium temperatures. 11 +85 c (default) 00 +70 c 01 +45 c 10 +15 c dpd 4 w deep power down enable/disable the dpd control bit puts the cellularram device in an extreme low power mode cutting current consumption to less than 25 a. stored memory data is not retained in this mode. though the settings of both control registers rcr and bcr are also stored during dpd. 0 dpd enabled 1 dpd disabled (default)
hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram functional description data sheet 22 v2.0, 2003-12-16 2.3.1 partial array self refresh (pasr) by applying pasr the user can dynamically customize the memory c apacity to one?s actual needs in normal operation mode and standby mode. with the activation of pasr there is no l onger a power penalty paid for the larger cellularram memory capacity in case only e.g. 8 mbits are used by the host system. bit2 down to bit0 specify the active memory array and its location (starting from bottom or top). the memory parts not used are powered down immediately after the mode r egister has been programmed. advice for the proper register setting including the address ranges is given in figure 9 . figure 9 pasr programming scheme pasr is effective in normal operation and sta ndby mode as soon as it has been configured by register programming. default setting is the entire memory array. figure 10 shows an exemplary pasr configuration where it is assumed that the application uses max. 8 mbit out of 32 mbit. pasr [2:0] w partial array self refresh the 3-bit pasr field is used to specify the active memory array. the active memory array will be kept periodically refreshed whereas the disabled parts w ill be e xcluded from refresh and previously stored data will get lost. the normal operation still can be executed in disabled array, but stored data is not guaranteed. this way the customer can dynamically adapt the memory capacity in steps of 8 mbit (4mbit at lowest) to one?s need without paying a power penalty. please refer to figure 9 . 000 entire memory array (default) 001 lower 1/2 of the memory array (16 mb) 010 lower 1/4 of the memory array (8 mb) 011 lower 1/8 of the memory array (4 mb) 100 zero 101 upper 1/2 of the memory array (16 mb) 110 upper 1/4 of the memory array (8 mb) 111 upper 1/8 of the memory array (4 mb) res 20, [18:8], 3 w reserved must be set to ?0? 1) w: write-only access field bits type 1) description 8m 8m 8m 8m 000000h 07ffffh 0fffffh 17ffffh 1fffffh 000 001 010 0 11 1fffffh 180000h 100000h 080000h 000000h 10 0 101 110 111 pasr.bit2,1,0 pasr.bit2,1,0 4m 8m 16m 32m 4m 8m 16m 0m
data sheet 23 v2.0, 2003-12-16 hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram functional description figure 10 pasr configuration example 2.3.2 deep power down mode to put the device in deep power down mode the dpd control bit must be asserted to low. once set into this extreme low power mode current consumption is cut down to less than 25 a. all internal voltage generators inside the cellularram are switched off and the internal self-refresh is stopped. this means that all stored memory information will be lost by entering dpd. only the register values of bcr and rcr are kept valid during dpd. to leave the deep power down mode again the refresh configuration register has to be accessed and the dpd bit has to be programmed to high level voltage. a guard time of at least 150 s has to be met where no commands beside a nop must be applied to re-enter again standby or idle mode. 2.3.3 temperature compensated self refresh (tcsr) the 2-bit wide tcsr field features four different temperature ranges to adjust the refresh period to the actual case temperature. dram technology requires higher refresh rates at higher temperature. at low temperature the refresh rate can be reduced, which reduces as well the standby current of the chip. this feature can be used in addition to par to lower power consumption in case of low or medium temperatures. please refer to table 10 . 2.3.4 power saving potential in standby when applying pasr, tcsr or dpd table 10 demonstrates the currents in standby mode when pasr, tcsr or dpd is applied. table 10 standby currents when applying pasr, tcsr or dpd operation mode power mode pasr bit controlled wake-up phase active array standby [ a] no operation/ deselect standby tcsr rcr.bit6-5 ? ? 85 70 45 15 pasr rcr.bit2-0 ? full 1/2 1/4 1/8 0 90(120) 80(105) 70(90) 60(75) 50(60) 75(100) 68(90) 62(80) 55(70) 50(60) 60(80) 56(75) 53(70) 52(65) 50(60) 50(60) 50(60) 50(60) 50(60) 50(60) dpd deep power down dpd rcr.bit4 ~150 s0 25.0 24mb deactivated 000000h 07ffffh rcr.bit 2,1,0= 01 0 active memory array defined by pasr to 8mb 8m activated 32mb cellularram
hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram functional description data sheet 24 v2.0, 2003-12-16 2.3.5 page mode enable/disable in asynchronous operation mode, the user has the option to enable page mode to toggle a0 - a3 in random way at higher cycle rate (20 ns vs. 70 ns) to lower access times of subsequent reads within 16-word boundary. write operation is not supported in the manner of page mode access. in synchronous mode, this option has no effect. the max. page length is 16 words, so which a0 - a3 is regarded as page-mode address. if the access needs to cross the boundary of 16-word (any difference in a20 - a4), then it should start over new random access cycle, which is the same as asynchronous read operation. please note that as soon as page mode is enabled the cs low time restriction applies. this means that the cs signal must not kept low longer than t csl = 10 s. please refer to figure 15 . pasr refreshed memory area a2 a1 a0 partial array self refresh 001 010 a0 entire memory array (def.) 000 a1 a2 a3 a4 a5 a6 a7 a8 a18 a20 tcsr pm 0 0 0 max. case temp. a5 temperature-compensated self-refresh 1 +85c (def.) +70c +45c +15c 0 1 0 a6 1 0 0 1 control reg control register select rcr bcr 0 1 a19 address bus control registe r power down deep power down mode enabled disabled (def.) 0 1 a4 011 lower 1/2 of memory array lower 1/4 of memory array lower 1/8 of memory array 101 110 111 upper 1/2 of memory array upper 1/4 of memory array upper 1/8 of memory array dpd 0 zero 100 page mode page mode bit disabled (def.) enabled 0 1 a7 a19 0 a20, a18....a8, a3: reserved, must be set to '0'. refresh control register (rcr)
data sheet 25 v2.0, 2003-12-16 hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram functional description 2.4 bus control register the bus control register (bcr) specifies the interface configurations. for the various configuration options please refer to the register description below. the bus control register is programmed via the control register set command (with cre = 1 and a19 = 1) and retains the stored information until it is reprogrammed or the device loses power. please note that the bcr contents can only be set or changed when the cellularram is in idle state. note: bit 9 must be set to ?0? and bit 6 to ?1? for proper operation. bcr bus control register (cre, a19 = 11 b ) a20a19a18a17a16a15a14a13a12a11a10a9a8a7a6a5a4a3a2a1a0 0 1 0 om 0 latency mode wp 0 wc 0 1 imp 0 bw burst length field bits type 1) description rs 19 w register select 1 set to 1 to select this bcr (= 0 to select rcr). op- mode 15 w operation mode the cellularram supports three different interface access protocols, the sram-type protocol with asynchronous read and write accesses the nor-flash-type protocol with synchronous read and asynchronous write accesses the full synchronous mode with synchronous read and synchronous write accesses operating the device in synchronous mode maximizes bandwidth. the nor-flash type mode is the recommended mode for legacy baseband systems which are not able to run the synchronous write protocol. the opmode bit defines whether the device is operating in synchronous (fully or partially) mode or asynchronous mode. 0 nor-flash-type mode read: synchronous burst mode write: asynchronous access mode 0 full synchronous mode read: synchronous burst mode write: synchronous burst mode the mode of write operation, nor-flash or full synchronous, is adaptively detected: this is done by detecting a rising clock edge during adv valid. if a rising clock edge occurs within adv valid, full synchronous write is detected. if there is no rising clock edge then nor flash write is detected. please refer to figure 22 on page 40 for asynchronous write and to figure 25 on page 43 for synchronous write. 1 sram-type mode (default) read: asynchronous access mode write: asynchronous access mode lat [13:11} w latency mode the latency mode has to be adjusted to the desired burst frequency. depending on the programmed latency, driving 1 st data output is delayed by the number of clock cycles as specified in this field counting from the address valid strobe signal, adv . 010 latency code 2, max 66 mhz burst clock frequency 011 latency code 3 (default), max 104 mhz burst clock frequency note: all others reserved.
hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram functional description data sheet 26 v2.0, 2003-12-16 wp 10 w wait polarity the wait polarity control bit allows the user to define the polarity of the wait output signal. the wait output line is used during a synchronous read burst to signal when the output data is invalid. 0 active low 1 active high (default) wc 8 w wait configuration the wait signal configuration control bit specifies whether the wait signal is asserted at the time of the delay or whether it is asserted one clock cycle in advance. 0 wait is asserted during the delay 1 wait is asserted one data cycl e before the delay (default) imp 5 w output impedance for adaptation to different system characteristics the output impedance can be configured. 0 full drive for 50 ? systems (default) 1 quarter drive bw 3 w burst wrap the burst wrap control bit defines whether there is a wrap around within a burst access or not. in case of fixed 8-word burst length, this means that after word7 , word0 is going to be output in wrap mode. in case of continuous burst mode the internal address counter will wrap from the last address, 1fffff h to 000000 h regardless of the setting. please note this setting is only used for burst read mode, since burst write mode is always continuous. 0wrap 1 no wrap (default) bl [2:0] w burst length (burst read only) via the burst length field the user can select between fixed burst lengths of 4, 8, and 16 and any arbitrary burst length by choosing the continuous mode option. in continuous mode the burst length is controlled by the active low period of the read control lines cs and oe . please note this setting is only used for burst read mode. burst write mode is always continuous independent of this register setting. 001 4-word burst 010 8-word burst 011 16-word burst 111 continuous (default) res 20, [18:16], 14, 9, 7, 4 w reserved must be set to ?0? 1) w: write-only access field bits type 1) description
data sheet 27 v2.0, 2003-12-16 hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram functional description 2.4.1 latency modes the latency mode defines the number of clock cycles which pass before the first output data is valid within a read burst access (counting from the clock edge where adv was detected low). the number of inserted wait cycles increases along with the input clock frequency. please refer to table 11 for the proper setting. please note that the first access delay might be extended by another 1-3 wait cycles in case the burst read or write access collides with an ongoing self-refresh operation. figure 11 latency mode - functional diagram table 11 latency mode configuration latency mode max. input clock frequency [mhz] -9.6 -12.5 -15 0 reserved reserved reserved 1 reserved reserved reserved 2665040 3 104 80 66 don't care dqx c ontrol read n clk nop nop nop q n+1 q n+2 q n+3 nop q n+4 nop q n+5 nop q n+6 nop q n+7 dqx q n+1 q n+2 q n+3 q n+4 q n+5 q n+6 q n+7 dqx q n+1 q n+2 q n+3 q n+4 q n+5 q n+6 q n+7 code0 (reserved) code1 (reserved) code2 code3 dqx q n+1 q n+2 q n+3 q n+4 q n+5 q n+6 q n+7
hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram functional description data sheet 28 v2.0, 2003-12-16 2.4.2 read burst configurations/sequences the numbers of words that are read during a burst read access is defined by the burst length field which is programmed in the bus control register. the user can eith er program fixed burst lengths of 4-words, 8-words or 16-words or operate the device in continuous mode operation. the burst start address is latched by adv set to low. an internal address counter then increments automatically the address with respect to the programmed burst length. continuous burst operation does not stop automatically though a row boundary has been reached. in other words, unlike with fixed burst lengths, a continuous burst goes on until it is actively terminated by bringing cs to high sampled at the valid edge of clk. the wrap mode option specifies whether the burst address overflows and restarts at address 0 (a3 - a0) or keeps incrementing. in continuous burst mode, the internal address counter wraps to 000000 h if the operation goes on past the last address, 1fffff h regardless of wrap mode setting. for the several possible burst sequences please refer to table 12 . the burst length is only configurable for burst read while burst write uses always continuous burst mode, independent of the burst length setting in the burst control register bcr. same for burst wrap, in burst write there is always the default - no wrap - used, independent on read burst register setting. table 12 burst sequences burst length starting address (a3 a2 a1 a0) sequential burst addressing scheme (decimal) wrap on wrap off 4xx00 xx01 xx10 xx11 0 1 2 3 1 2 3 0 2 3 0 1 3 0 1 2 0 1 2 3 1 2 3 4 2 3 4 5 3 4 5 6 8 x000 x001 x010 x011 x100 x101 x110 x111 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9 3 4 5 6 7 8 9 10 4 5 6 7 8 9 10 11 5 6 7 8 9 10 11 12 6 7 8 9 10 11 12 13 7 8 9 10 11 12 13 14 16 0000 0001 0010 ? ? 1101 1110 1111 0 1 2 ? 13 14 15 1 2 3 ? 14 15 0 2 3 4 ? 15 0 1 ? ? 13 14 15 ? 10 11 12 14 15 0 ? 11 12 13 15 0 1 ? 12 13 14 0 1 2 ? 13 14 15 1 2 3 ? 14 15 16 2 3 4 ? 15 16 17 ? ? 13 14 15 ? 26 27 28 14 15 16 ? 27 28 29 15 16 17 ? 28 29 30 continuous n cn, cn+1, cn+2, ? cmax 1) , 0, 1, ? (default, write burst) 1) cmax = 1fffff h
data sheet 29 v2.0, 2003-12-16 hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram functional description 2.4.3 wait signal in synchronous burst mode the wait signal is used in synchronous burst read mode to indicate to the host system when the output data is invalid. periods of invalid output data within a burst access might be caused either by first access delays, by delays induced by row boundary crossings or by self-refresh cycles. to match with the flash interfaces of different microprocessor types the polarity and the timing of the wait signal can be configured. the polarity can be programmed to either active low or active high logic. the timing of the wait signal can be adjusted as well. depending on the bcr setting the wait signal will be either asserted at the same time the data becomes invalid or it will be set active already one clock period in advance. in asynchronous read mode including page mode, the wait signal is not used but always stays asserted as bcr bit 10 is specified. in this case, system should ignore wait state, since it does not reflect any valid information of data output status. 2.4.4 hold data out mode the configuration of hold data out mode is not supported. please note that valid data is held always for one clock cycle. figure 12 data out configuration 2.5 self-refresh the cellularram relieves the host system from triggering and commanding refresh-operations like it is the case with conventional drams by performing automatic self-refresh. self-refresh operations are autonomously scheduled and performed by the cellularram device. dq15-dq0 clk wait q0 q1 q2 q3 q4 q5 bcr.wc=1: bcr.wc=0: wait bcr.wp= 0 bcr.hdo= 1 bcr.wp= 0 bcr.hdo= 0 not supported don't care
hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram functional description data sheet 30 v2.0, 2003-12-16 burst length length a2 a1 a0 all others reserved continuous (def) 111 burst length 8 010 a0 4 001 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 bw 0 0 wp wc imp 0 om control reg control register select selects rcr selects bcr 0 1 a19 drive strength output impedance full drive (def) 1/4 drive 0 1 a5 latency mode latency all others reserved latency mode 001 reserved 000 reserved code3 (def) 011 polarity wait polarity active low active high (def) 0 1 a10 opmode operation mode sync mode 0 1 a15 address bus control registe r 16 011 timing wait configuration at delay one data cycle in advance (def) 0 1 a8 async./ page mode (def) wrap mode burst wrap wrap no wrap (def) 0 1 a3 a11 a12 a13 a19 1 code2 010 (note) a9 must be set to ?0? for proper operation 0 1 (note) a6 must be set to ?1? for proper operation bus control register (bcr)
data sheet 31 v2.0, 2003-12-16 hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram functional description 2.6 sram-type mode in sram-type mode the cellularram applies the standard asynchronous sram protocol to perform read and write accesses. 2.6.1 asynchronous read after power-up the cellularram operates per default in asynchronous sram-type mode. the synchronous clock line, clk has to be held low, while address latch signal, adv can be held low for entire read and write operation in this mode or toggled to latch valid address input (refer to ?asynchronous write with address latch (adv) control? on page 40 for details). wait is always asserted as bcr. bit 10 is programmed, so that the controller should ignore wait during asynchronous mode operation. reading from the device in asynchronous mode is accomplished by asserting the chip select (cs ) and output enable (oe ) signals to low while forcing write enable (we ) to high. if the upper byte (ub ) control line is set active low then the upper word of the addressed data is driven on the output lines, dq15 to dq8. if the lower byte (lb ) control line is set active low then the lower word of the addressed data is driven on the output lines, dq7 to dq0. the access time is determined by the triggering input - slowest one in low-going transition - among valid address ( t aa ), cs ( t co ), oe ( t oe ), ub or lb ( t ba ), or adv ( t aadv ). figure 13 asynchronous read - address controlled (cs = oe = v il , we = v ih , ub and/or lb = v il , cre = v il, adv = v il ) figure 14 asynchronous read (we = v ih , cre = v il ) not valid a20-a0 address data valid dq15-dq0 previous data t oh t aa t rc don't care a20-a0 address cs ub, lb oe data valid we d q15-dq0 t co t aa t ba t oe t blz t oh t oh z t bhz t rc t olz t lz t cph t hz t bph adv t vph t aadv
hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram functional description data sheet 32 v2.0, 2003-12-16 2.6.2 page mode if activated by rcr.bit7 page mode allows to toggle the f our lower address bits (a3 to a0) to perform subsequent random read accesses (max. 16-words by a3 - a0) at much faster speed than 1 st read access. page mode operation supports only read access in cellularram. as soon as page mode is activated, cs low time restriction ( t csl ) applies. in case of cs staying low longer than t csl limit, then it is alternative way to toggle non-page address (a20 - a4) no later than t csl,max . therefore the usage of page mode is only recommended in systems which can respect this limitation. adv has to be held low for entire page operation. please see also application note on page 50 . figure 15 asynchronous page read mode (cre = v il, adv = v il ) don't care a20-a4 address cs ub, lb oe we d q15-dq0 t co t lz t blz t bhz t ohz t rc a3-a0 address t aa data adr adr adr adr t oh t csl t olz t hz t pc data data data data t paa
data sheet 33 v2.0, 2003-12-16 hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram functional description table 13 timing parameters - asynchronous read parameter symbol 9.6, 12.5 15 unit notes min. max. min. max. read cycle time t rc 70 ? 85 ? ns ? address access time t aa ?70?85ns? adv access time t aadv ?70?85ns? adv high time t vph 5?7?ns? page address cycle time t pc 20 ? 25 ? ns ? page address access time t paa ?20?25ns? output hold from address change t oh 5?6?ns? chip select access time t co ?70?85ns? ub , lb access time t ba ?70?85ns? oe to valid output data t oe ?20?25ns? chip select pulse width low time t csl ?10?10 s? chip select to output active t lz 6?6?ns? chip select disable to high-z output t hz ?8?8ns? ub , lb enable to output active t blz 6?6?ns? ub , lb disable to high-z output t bhz ?8?8ns? output enable to output active t olz 3?3?ns? output disable to high-z output t ohz ?6?8ns? cs high time when toggling t cph 10 ? 15 ? ns ? ub , lb high time when toggling t bph 10 ? 15 ? ns ?
hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram functional description data sheet 34 v2.0, 2003-12-16 2.6.3 asynchronous write writing to the device in asynchronous sram mode is accomplished by asserting the chip select (cs ) and write enable (we ) signals to low. adv can be used to latch the address (refer to ?asynchronous write with address latch (adv) control? on page 40 for details) or simply held low for entire write operation. if the upper byte (ub ) control line is set active low then the upper word (dq15 to dq8) of the data bus is written to the specified memory location. if the lower byte (lb ) control line is set active low then the lower word (dq7 to dq0) of the data bus is written to the specified memory location. write operation takes place when either one or both ub and lb is asserted low. the data is latched by the rising edge of either cs , we , or ub /lb whichever signal comes first. figure 16 asynchronous write - we controlled (oe = v ih or v il , cre = v il ) figure 17 asynchronous write - cs controlled (oe = v ih or v il , cre = v il ) don't care a20-a0 address cs we ub, lb dqx in t cw t wr t wc t wp t aw t bw data valid d qx out t dw t dh t as t whz t ow adv t vph t vs t wph don't care a20-a0 address cs we ub, lb d qx out t cw t wc t as t wp t dw t dh t bw data in valid dqx in high-z t lz, t blz t whz adv t cph t wr t aw t vph t vs
data sheet 35 v2.0, 2003-12-16 hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram functional description figure 18 asynchronous write - ub , lb controlled (oe = v ih or v il , cre = v il ) the programming of control register in sram-type mode is performed in the similar manner as asynchronous write except cre being held high during the operation. note that cre has to meet set-up ( t cres ) and hold time ( t creh ) of valid state (= high) in reference to we falling and rising edge, respectively. adv may be kept low for entire operation. cs should toggle at the end of the operation to get ready for following access. figure 19 asynchronous write to control register (oe = v ih or v il ) don't care a20-a0 address cs we ub, lb d qx out t cw t wc t as t wp t bw data in valid dqx in t dw t dh high-z t blz, t lz t whz adv t bph t wr t aw t vph t vs don't care a20-a0 opcode cs we ub, lb d qx out t cw t wr t wc t wp t aw dqx in t as t creh t cres t lz, t blz t whz high-z a19 cre adv t vph 0(rcr), 1(bcr) high-z t wph t aw
hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram functional description data sheet 36 v2.0, 2003-12-16 table 14 timing parameters - asynchronous write parameter symbol 9.6, 12.5 15 unit notes min. max. min. max. write cycle time t wc 70 ? 85 ? ns ? address (incl. cre) set-up time t as 0?0?ns? address valid to end of write t aw 70 ? 85 ? ns ? write recovery time t wr 0?0?ns? chip select pulse width low time t csl ?10?10 s? chip select to end of write t cw 70 ? 85 ? ns ? adv high time t vph 5?7?ns? adv setup to end of write t vs 70 ? 85 ? ns ? byte control valid to end of write t bw 70 ? 85 ? ns ? write pulse width t wp 40 ? 45 ? ns ? write pulse pause t wph 10 ? 15 ? ns ? cs high time when toggling t cph 10 ? 15 ? ns ? ub , lb high time when toggling t bph 10 ? 15 ? ns ? write to output disable t whz ?8?10ns? end of write to output enable (oe = low) t ow 3?3?ns? write data setup time t dw 20 ? 20 ? ns ? write data hold time t dh 0?0?ns? cre setup time (to we = ce = low) t cres 5?5?ns? cre hold time (from we high) t creh 0?0?ns?
data sheet 37 v2.0, 2003-12-16 hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram functional description 2.7 nor-flash-type mode in nor-flash mode the cellularram applies the nor-flash protocol to perform read and write accesses to the memory. read accesses can be executed in synchronous burst mode, while write accesses are executed in asynchronous mode using adv as address latch strobe signal. 2.7.1 synchronous read mode [disclaimer] wait signal of all synchronous timings below is shown in the case of wc=0 (at delay) and wp=0 (active low) though it is not default state. in synchronous read mode all operations are referred to the rising or falling clock signal edge. refresh cycles or page boundary crossings are indicated by the wait output signal which stalls the processor for this period. figure 20 synchronous read burst don't care cs oe ub, lb we d q15-dq0 t hd t od a20-a0 q0 adr clk wait adv t sp t vph t css q2 q3 q4 t clk t ckh t ckl t koh t wk q1 in case the burst read access collides with an ongoing refresh cycle additional wait cycles might be inserted latency code2 t sp t vp t aba t cbph t ol t cwt t wz t aclk t sp t hd t hd t aoe while row boundary crossing occurs, wait is asserted t hd
hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram functional description data sheet 38 v2.0, 2003-12-16 2.7.2 burst suspend while in synchronous burst operation, the bus interface may need to be assigned to other memory transaction sharing the same bus. burst suspend mode is used to fulfill this operation. keeping cs low (wait stays asserted indicating valid data output on dq pins, though they are tri-stated), burst suspend can be initiated with halted clk. clk can stay at either high or low state. as specified, duration of keeping cs low can not exceed t csl maximum, which is 10 s, so that internal refresh operation is able to run properly. in this event of exceeding t csl maximum, termination of burst by bringing cs to high is strongly recommended instead of using burst suspend mode, then reissuing of the discontinued burst command is required. figure 21 burst suspend don't care cs oe ub, lb we d q15-dq0 t aoe t hd t od a20-a0 q0 adr clk wait adv t sp t vph t css q1 q2 q3 t clk t ckh t ckl t koh t wk q1 latency code2 t sp t vp t aba t cbph t ol t cwt t wz t aclk t sp t hd t hd t od t aoe burst suspend /cs low time in burst suspend should not exceed 10us for internal refresh operation. t csl *1 *1: in case /oe being held low, q1 is maintained on dq
data sheet 39 v2.0, 2003-12-16 hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram functional description table 15 timing parameters - synchronous read burst parameter symbol 9.6 12.5 15 unit notes min. max. min. max. min. max. clock period frequency lat = 3 f clk3 ? 104 ? 80 ? 66 mhz ? lat = 2 f clk2 ?66?50?40mhz? clock period lat = 3 t clk3 9.6 ? 12.5 ? 15 ? ns ? lat = 2 t clk2 15?20?25?ns? clock high time t ckh 3?3.5?4?ns? clock low time t ckl 3?3.5?4?ns? clock rise/fall time t t ?1.8?2?2ns? input setup time to clk (except cs ) t sp 3?3.5?4?ns? input hold time from clk t hd 1.5?2?2?ns? adv pulse width high t vph 5?5?7?ns 1) adv pulse width low t vp 4?4?6?ns? burst read 1 st access delay from clk t aba ? 35 ? 46.5 ? 54 ns 2) cs low setup to clk t css 3.5 20 4 20 4 20 ns 3) chip select pulse width low time t csl ?10?10?10 s? cs pulse width high t cbph 5?6?8?ns? oe or lb /ub low to output low-z t ol 3?3?3?ns? cs , oe , or lb /ub high to output high-z t od 060808ns? oe low to output delay t aoe ?20?20?25ns? cs low to wait valid t cwt ?7?9?11ns? cs high to wait high-z t wz 070808ns? clk to wait valid t wk ?7?9?11ns? clk to output delay t aclk ?7?9?11ns? output hold from clk t koh 2?2?3?ns? 1) adv low for new burst command can not be issued while the previous burst is in burst_init cycle (within latency). 2) in case of refresh collision to the first access, more wait cycles will be added. 3) for proper synchronous burst operation, t cssmax should be met. otherwise, it is strongly recommended to use cellularram in asynchronous mode of operation, instead.
hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram functional description data sheet 40 v2.0, 2003-12-16 2.7.3 asynchronous write with address latch (adv ) control in asynchronous write mode, the synchronous clock is switched off and clk has to be held low. the access protocol is shown with adv -latching scheme and it can be applied to write operation in sram-type mode. figure 22 asynchronous write with address latch (adv ) control (followed by single-burst read) figure 23 asynchronous write with address latch (adv ) control don't care a20-a0 address cs we ub, lb data input oe d q15-dq0 t cw t wp t ds t dh t vp adv t vph t avs t avh t wph t cka t wc t vs t bw t as t wr t aw q0 adr t css t wk latency code2 t vp t aba t ol t cwt t aclk t sp t hd t cph wait t od t cbph t wz t aoe t koh t hd t sp t sp t hd clk don't care a20-a0 cs we ub, lb oe d q15-dq0 adv address data input t cw t wp t ds t dh t vp t avs t avh t wph t wc t vs t bw t as t wr t aw
data sheet 41 v2.0, 2003-12-16 hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram functional description the programming of control register in nor-flash-type mode is performed in the similar manner as asynchronous write with adv control except cre being held high during the code input operation. note that cre has to meet set-up ( t crs ) and hold time ( t crh ) of valid state (= high) in reference to adv rising edge. adv may be kept low for entire operation or go high to latch valid control register information at its rising edge. figure 24 asynchronous write to control register in nor-flash mode table 16 timing parameters - asynchronous write with adv control parameter symbol 9.6, 12.5 15 unit notes min. max. min. max. we high to clk valid t cka 25?35?ns? write cycle time t wc 70?85?ns? address setup time to write start t as 0?0?ns? address setup to adv high t avs 10?10?ns? address hold from adv high t avh 5?5?ns? address to end of write t aw 70?85?ns? adv pulse width high t vph 8?10?ns? adv pulse width low t vp 8?10?ns? adv setup to end of write t vs 70?85?ns? cs to end of write t cw 70?85?ns? ub /lb to end of write t bw 70?85?ns? write pulse width low t wp 40?45?ns? write pulse width high t wph 10?15?ns? cs high time (synch_read) t cbph 5?8?ns? don't care a20-a0 opcode cs we ub, lb oe d q15-dq0 t cw t wp t vp adv address t vph t avs t avh t wph t cka t wr t wc t vs cre a19 t crs t crh 0(rcr), 1(bcr) t aw clk
hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram functional description data sheet 42 v2.0, 2003-12-16 note: 1. t wr is valid only when adv latch of address does not take place until the end of write. cs high time (asynch_write, mixed) t cph 10?15?ns? write recovery time t wr 0?0?ns1 data setup to we high t ds 20?20?ns? data hold from we high t dh 0?0?ns? cre setup to adv high t crs 10?10?ns? cre hold from adv high t crh 5?5?ns? table 16 timing parameters - asynchronous write with adv control (cont?d) parameter symbol 9.6, 12.5 15 unit notes min. max. min. max.
data sheet 43 v2.0, 2003-12-16 hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram functional description 2.8 synchronous mode [disclaimer] wait signal of all synchronous timings below is shown in the case of wc=0 (at delay) and wp=0 (active low) though it is not default state. in synchronous mode, read and write operations are synch ronized to the clock. refresh cycles or page boundary crossings are indicated to the host system by asserting t he wait signal which in turn stalls the processor. wait polarity, wait timing, synchronicity to the falling/rising clock edge, the burst length and further options are user configurable and can be programmed via the bus configuration register (bcr). 2.8.1 synchronous read mode including burst suspend refer to section 2.7.1 and section 2.7.2 . all the timing and parameters are same as described in read operation for nor-flash-type mode. 2.8.2 synchronous write mode in synchronous write mode, ub and lb are used as byte control of data input mask. at the rising edge of clk, their state is sampled and determined whether the coupled byte (dq15-8 for ub and dq7-0 for lb ) is updated by input data. proper set-up time and hold time to clk should be met. as discussed in section 2.4 , synchronous burst write is always configured as continuous and no wrap, so that it has to be terminated by cs high state after the burst fulfills required length of cycles. figure 25 synchronous write burst hi-z don't care cs oe ub, lb we d q15-dq0 t hd a20-a0 adr clk wait adv t sp t css t clk t ckh t ckl t hd t hd in case the burst write access co llides with an ongoing refresh cycle additional wait cycles might be inserted d0 d1 d2 d3 d4 t wz t cbph t wk t cwt latency code2 t sp t hd (mask) t vp t vph t hd t sp t sp t sp
hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram functional description data sheet 44 v2.0, 2003-12-16 figure 26 synchronous write to control register hi-z don't care cs oe ub, lb we d q15-dq0 a20-a0 opcode clk wait adv t clk t ckh t ckl t wz cre a19 t hd t sp t css t cwt t hd t sp 0(rcr), 1(bcr) t hd t sp t sp t hd t hd t sp (wait for twcmin for new command cycle) t hd
data sheet 45 v2.0, 2003-12-16 hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram functional description figure 27 synchronous write burst followed by synchronous read burst figure 28 synchronous read burst followed by synchronous write burst hi-z don't care cs oe ub, lb we d q15-dq0 a20-a0 clk wai t adv t clk t ckh t ckl in case the burst write access collides with an ongoing refresh cycle additional wait cycles might be inserted d0 d1 d2 d3 t wz t cbph t wk t cwt latency code2 adr t aoe t hd t od q0 adr t sp t css q2 q3 t koh t wk q1 latency code2 t vp t aba t cbph t ol t cwt t wz t aclk t hd t sp t hd t hd t hd t sp t hd t sp t css t hd t sp t vp (hi-z) don't care cs oe ub, lb we d q15-dq0 a20-a0 clk wait adv t css in case the burst access collides with an ongoing refresh cycle additional wait cycles might be inserted d0 d1 d2 d3 t wk t cwt latency code2 t wz t od q0 adr t vph t css q2 q3 t clk t ckh t ckl t koh t wk q1 latency code2 t aba t cbph t ol t cwt t wz t aclk t sp t hd t hd t aoe t sp t hd t vp adr t hd t vp t sp t sp t hd t hd t hd t sp
hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram functional description data sheet 46 v2.0, 2003-12-16 2.9 general ac input/output reference waveform the input timings refer to a midlevel of v ddq /2 while as output timings refer to midlevel v ddq /2. the rising and falling edges are 10 - 90% and < 2 ns. table 17 timing parameters - synchronous read/write burst parameter symbol 9.6 12.5 15 unit notes min. max. min. max. min. max. clock period frequency lat = 3 f clk3 ? 104 ? 80 ? 66 mhz ? lat = 2 f clk2 ?66?50?40mhz? clock period lat = 3 t clk3 9.6 ? 12.5 ? 15 ? ns ? lat = 2 t clk2 15?20?25?ns? clock high time t ckh 3?3.5?4?ns? clock low time t ckl 3?3.5?4?ns? clock rise/fall time t t ?1.8?2?2ns? input setup time to clk (except cs ) t sp 3?3.5?4?ns? input hold time from clk t hd 1.5?2?2?ns? adv pulse width high t vph 5?5?7?ns 1) adv pulse width low t vp 4?4?6?ns? burst read 1 st access delay from clk t aba ? 35 ? 46.5 ? 54 ns 2) cs low setup to clk t css 3.5 20 4 20 4 20 ns 3) chip select pulse width low time t csl ?10?10?10 s? cs pulse width high t cbph 5?6?8?ns? oe or lb /ub low to output low-z t ol 3?3?3?ns? cs , oe , or lb /ub high to output high-z t od 060808ns? oe low to output delay t aoe ?20?20?25ns? cs low to wait valid t cwt ?7?9?11ns? cs high to wait high-z t wz 070808ns? clk to wait valid t wk ?7?9?11ns? clk to output delay t aclk ?7?9?11ns? output hold from clk t koh 2?2?3?ns? 1) adv low for new burst command can not be issued while the previous burst is in burst_init cycle (within latency). 2) in case of refresh collision to the first access, more wait cycles will be added. 3) for proper synchronous burst operation, t cssmax should be met. otherwise, it is strongly recommended to use cellularram in asynchronous mode of operation, instead.
data sheet 47 v2.0, 2003-12-16 hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram electrical characteristics 3 electrical characteristics 3.1 absolute maximum ratings attention: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. 3.2 recommended power & dc operation ratings all values are recommended operating conditions unless otherwise noted. table 18 absolute maximum ratings parameter symbol limit values unit notes min. max. operating temperature range t c -25 +85 c ? storage temperature range t stg -55 +150 c ? soldering peak temperature (10 s) t sold ?260c? voltage of v dd supply relative to v ss v dd -0.3 +2.45 v ? voltage of v ddq supply relative to v ss v ddq -0.3 +3.6 v ? voltage of any input relative to v ss v in -0.3 +3.6 v ? power dissipation p d ?180mw? short circuit output current i out -50 +50 ma ? table 19 recommended dc operating conditions parameter symbol limit values unit notes min. typ. max. power supply voltage, core v dd 1.7 1.8 1.95 v ? power supply voltage, 1.8 v i/os v ddq 1.7 1.8 2.25 v ? input high voltage v ih v ddq ? 0.4 ? v ddq + 0.2 v ? input low voltage v il -0.2 ? 0.4 v ? table 20 dc characteristics parameter symbol limit values unit notes min. typ. max. output high voltage ( i oh = -0.2 ma) v oh v ddq 0.8 ? ? v ? output low voltage ( i ol = 0.2 ma) v ol ?? v ddq 0.2 v ? input leakage current i li ??1 a? output leakage current i lo ??1 a?
hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram electrical characteristics data sheet 48 v2.0, 2003-12-16 3.3 output test conditions figure 29 output test circuit please refer to section section 2.9 . 3.4 pin capacitances table 21 operating characteristics parameter symbol 9.6 12.5 15 unit test condition notes min. max. min. max. min. max. operating current async read/write random @ t rcmin async read/write random @ t rc =1 s async page read sync burst (continuous) burst initial access i dd1 i dd1l i dd1p i dd4 i dd5 ? ? ? ? ? 20 5 15 20 35 ? ? ? ? ? 20 5 15 18 35 ? ? ? ? ? 17 5 12 15 30 ma v in = v dd or v ss , chip enabled, i out = 0 1) stand-by current : l-part i dd2 ?90?90?90 a v in = v dd or v ss ,chip deselected, (full array) ? stand-by current : standard ? 120 ? 120 ? 120 a? deep power down current i dd3 ? 25? 25? 25 a v in = v dd or v ss ? 1) the specification assumes the output disabled. table 22 pin capacitances pin limit values unit condition min. max. a20 - a0, cs , oe , we , ub , lb , cre, adv ?5.0pf t a = +25 c freq. = 1 mhz v pin = 0 v (sampled, not 100% tested) clk ? 5.0 pf dq15 - dq0 ? 6.0 pf wait ? 6.0 pf 30pf test poin t vddq dut 5.4kohm 5.4kohm
data sheet 49 v2.0, 2003-12-16 hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram package outlines 4 package outlines figure 30 p-vfbga-54 (plastic very thin fine pitch ball grid array package) s md = surface mounted device y ou can find all of our packages, sorts of packing and others in our i nfineon internet page ?products?: http://www.infineon.com/products . dimensions in m m
hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram appendix a: low-frequency mode data sheet 50 v2.0, 2003-12-16 5 appendix a: low-frequency mode 5.1 asynchronous access depending on the random access frequency two cases are distinguished: high frequency mode ( 100 khz): there are no t rc max. time nor cs /oe max. low time restrictions during subsequent random read or write accesses. low frequency mode (< 100 khz): there are no t rc max. time nor cs /oe max. low time restrictions if all control signals (cs , oe , we , ub /lb ) follow the modified timing as shown below, see attached timing diagram and timing table. there is no extra mode register setting necessary. figure 31 low-frequency mode parameter symbol 9.6, 12.5 15 unit notes min. max. min. max. address stable time for read access t arv 70 ? 85 ? ns ? address stable overlap with write pulse t awv 70 ? 85 ? ns ? write pulse width t wpv 70 ? 85 ? ns ? data to write time overlap t dwv 70 ? 85 ? ns ? a20-a0 address cs t aa we data valid data valid t arv t awv t wpv t dwv d q<15:0>
data sheet 51 v2.0, 2003-12-16 hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram appendix b: s/w register entry mode (?4-cycle method?) 6 appendix b: s/w register entry mode (?4-cycle method?) other than cre-controlled scr operation, cellularram supports software (s/w) method as an alternative to access the control registers. since s/w register entry m ode consists of 4 consecutive access cycles to top memory location (all addresses are ?1?), it is often referred as ?4-cycle method?. 4-cycles starts from 2 back-to-back read cycles (initializing command identification) followed by one write cycl e (command identification completed and which control register is accessed is known), then final write cycle for configuring the selected control register by the given input or read cycle to check the content of the register thr ough dq pins. it does f unction the configuration of control register bits like the way with dedicated pin, cre method, but there are a few differences from cre- controlled method as follow; register read mode (checking content) is supported with s/w register entry as well as register write (program). the mode bits for control register are supplied through dq <15:0> instead of address pins in cre-controlled. though each register has 21-bits (a<20:0>) for 32m cellularram, only low 16-bit registers becomes valid during s/w method. only asynchronous read and write is allowed for consecutive 4 access cycles to top address. no synchronous timing is supported. if this entry mode is used in synchronous mode, then clock should stop running and stay at low level. instead of a19 bit state, the selection of which control register, bcr or rcr, is done with the state of dq<15:0> given at 3rd cycle. (?00h? for rcr, ?01h? for bcr) since s/w register entry asks for 4 complete access cycles in a row and the device is designed operating with internally regulated supply which is going to be discharged in deep power-down (dpd) mode, dpd function is not supported with this programming method. the method is realized by the dev ice exactly when 2 cons ecutive read cycles to top memory location is followed by write cycle to the same location, so that any exceptional cycle combination - not only access mode, but also the number of cycles - will fail in invoking the register entry mode properly. figure 32 s/w register entry timing (address input = 1fffffh) don't care amax-a0 all ?1?s cs ub, lb oe we dq15-dq0 t rc adv# all ?1?s all ?1?s 0000h(rcr) or 0001h( bcr) all ?1?s ` register bits read to top memory location (1 st ) read to top memory location (2nd) write to top memory location write or read to top memory location (cycle type) (function) wait for next write to confirm s/w register entry sel ect rcr or bcr (write) configure selected register by dq inputs (read) output selected register contents through dq t wc
hye18p32160ac(-/l)9.6/12.5/15 32m synchronous burst cellularram appendix b: s/w register entry mode (?4-cycle method?) data sheet 52 v2.0, 2003-12-16 figure 33 rcr mapping in s/w register entry figure 34 bcr mapping in s/w register entry pasr refreshed memory area d2 d1 d0 partial array self refresh 001 010 d0 entire memory array (def.) 000 d1 d2 d3 d4 d5 d6 d7 d8 d15 tcsr pm 0 0 max. case temp. d5 temperature-compensated self-refresh 1 +85c (def.) +70c +45c +15c 0 1 0 d6 1 0 0 1 dq<15:0> control registe r power down deep power down mode disabled (def.) x d4 011 lower 1/2 of memory array lower 1/4 of memory array lower 1/8 of memory array 101 110 111 upper 1/2 of memory array upper 1/4 of memory array upper 1/8 of memory array dpd* 0 zero 100 page mode page mode bit disabled (def.) enabled 0 1 d7 d15....d8, d3: reserved, must be set to '0'. burst length length d2 d1 d0 all others reserved continuous (def) 111 burst length 8 010 d0 4 001 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 bw 0 0 wp wc imp 1 0 om wrap mode output impedance full drive (def) 1/4 drive 0 1 d5 latency mode latency all others reserved latency mode 001 reserved 000 reserved code3 (def) 011 polarity wait# polarity active low active high (def) 0 1 d10 opmode operation mode sync mode 0 1 d15 dq <15:0> control registe r 16 011 0 timing wait# configuration at delay one data cycle in advance (def) 0 1 d8 async./ page mode (def) wrap mode burst wrap wrap no wrap (def) 0 1 d3 d11 d12 d13 code2 010
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